Added and improved architecture support:$$$added support for MSP430/MSP430X architecture; as the first interpreted ISA in Renode$$$ARM$$$added automatic connection of all ARM-A/R CPUs to GIC$$$added new registers for Cortex-A55$$$added definitions of Cortex-R5 specific CP15 registers$$$added TrustZone support for ARMv8-M$$$added FEAT_IDST support$$$added Thumb2 support on ARMv8$$$added support for 32-bit code in EL0$$$added ability to choose whether to emulate PSCI conduit with SMC or HVC$$$exposed 64 bit VFP registers$$$fixed RBAR/RLAR aliases by adding offset to the current region number$$$fixed a crash on not-completely initialized MMU mode$$$fixed issues with registers affecting code translation$$$fixed handling of the GE flag in sadd{8;16}; ssub{8;16}; usub{8;16} instructions$$$fixed Cortex-A78 core number value$$$fixed accessing 64-bit CSRs$$$fixed section descriptor decoding in LPAE$$$fixed PMSAv8 MPU control register behavior$$$fixed Cortex-M FPU context saving upon an IRQ$$$fixed swapping low and high portions of FPU registers on exception entry; when lazy preservation is not enabled$$$fixed wrong TB size reported for some Thumb instructions$$$fixed GICv3 CPU system registers incorrectly being enabled for older GIC versions$$$fixed access to system registers in 32-bit mode on a 64-bit core$$$fixed VFP instructions in 32-bit EL0 with 64-bit EL1$$$fixed a crash when performing a TLB fill while executing AArch32 code in certain conditions$$$fixed incorrect reporting of the IL field in the syndrome of data aborts taken to Hyp mode$$$fixed low bits of ATS1CP[RW] incorrectly treated as flags in the result (PAR) register$$$fixed handling of scalar VMOV$$$fixed the Thumb flag being set in block flags in traces in A64 state in some circumstances$$$changed lda/stl instructions on Armv8-M to not require address reservations as they are not exclusive$$$fixed PC synchronization in AArch64 state$$$improved SMC calls emulation$$$added non-secure aliases for v8 MPU (TrustZone)$$$reduced the verbosity of sysreg-related logs$$$RISC-V$$$$$$improved handling of the MSTATUS.FS flag$$$improved parsing of ISA strings to support more granular extension descriptions and custom extensions$$$fixed setting of the mtval register with the opcode that caused an exception$$$various fixes in Zb* Bit Manipulation instructions$$$fixed atomic LR/SC instructions$$$fixed incorrect log messages resulting from all-zero instruction translation$$$fixed the vmsbc instruction$$$fixed extension checking for compressed float load/store$$$added handling of the RV32E base integer instruction set in cpuType string parsing$$$added mirroring of the MCAUSE fields MPP and MPIE to MSTATUS in CLIC mode$$$added support for the Zacas extension for performing atomic Compare-and-Swap (CAS) operations$$$added support for Zve* and Zvfh vector extensions$$$added support for single vector trapping in selected SPARC cores$$$$$$added mechanism for dynamic ACPI table generation in X86$$$$$$added initial SMP support for x86$$$$$$added initial x86 KVM-based CPU support$$$$$$Added and improved platform descriptions:$$$$$$ZynqMP UltraScale+ with ZCU102 and ZCU104 boards$$$Renesas RZ/G2L$$$Silicon Labs Series-2- xG24; xG26; xG22 with a range of peripherals; including xG24 radio$$$BeagleV Fire$$$Polarfire SoC with Icicle Kit$$$Atmel SAM4S8B$$$Atmel SAM4S16C with SAM4S XPLAINED$$$Atmel SAMD21J17D$$$NXP IMXRT500$$$NXP Layerscape lx2160ardb$$$Nuvoton NPCX9$$$UP Squared$$$Virtualized x86 KVM$$$LiteX-based platforms$$$Added demos:$$$$$$MSP430F2619 Hello World demo$$$BeagleV-Fire booting up Linux Buildroot$$$Contiki-NG Hello World demo for Zolteria Z1$$$Web server running in Docker on ZynqMP$$$SAM4S series based demo running Zephyr shell sample$$$i386 KVM Linux demo$$$i386 KVM U-Boot demo$$$Renesas RZ/G2L Linux demo$$$Renesas RZ/G2L U-Boot based demo$$$lx2160ardb U-Boot based demo$$$IMXRT500 demo running Zephyrs shell_module sample$$$UP Squared demo running Zephyrs hello_world sample$$$NXP S32K388 demo running Zephyrs shell module sample$$$VeeR_EL2 Tock OS demo$$$Added tests:$$$

Added and improved architecture support:$$$$$$fixed Arm MPU skipping access checks for MPU regions sharing a page with a background region$$$FPU dirty flag is now set on all FPU load instructions for RISC-V$$$fixed Arm PMSAv8 not checking for domains not being page aligned$$$RISC-V MTVAL register now contains the invalid instruction after illegal instruction exception$$$Arm SRS (Store Return State) instruction now saves onto stack SPSR instead of masked CPSR$$$improved support for x86-64; verified with Zephyr$$$added SMEPMP extension stub for RISC-V$$$added ability to configure usable bits in RISC-V PMPADDR registers$$$fixed runtime configurability of the RISC-V MISA registers$$$fixed RISC-V PMPCFG semantics from WIRI to WARL$$$fixed decoding of C.ADDI4SPN in RISC-V$$$fixed behavior of RORIW; RORI and SLLI.UW RISC-V instructions$$$changed MSTATUS RISC-V CSR to be more responsive to the presence of User and Supervisor modes$$$Added and improved platform descriptions:$$$$$$NXP MR-CANHUBK3$$$NXP S32K388$$$NXP S32K118$$$RI5CY$$$Renesas r7fa8m1a$$$Renesas DA14592$$$STM32H743$$$x86-64 ACRN$$$Added demos and tests:$$$$$$Zephyr running hello_world demo on x86-64 ACRN$$$ZynqMP demo showcasing two way communication between Cortex-A53 running Linux and Cortex-R5 running OpenAMP echo sample$$$Added features:$$$$$$Socket Manager mechanism; organizing socket management in a single entity$$$test real-time timeout handling mechanism in Robot$$$GPIO events support for the External Control API$$$Zephyr Mode support for Arm; Arm-M; SPARC; x86 and Xtensa$$$disassembling support for x86-64 architecture$$$support for bus access widths other than DoubleWord for DPI integration of APB3$$$support for overriding a default implementation of the verilated UART model$$$Changed:$$$$$$improved renesas-segger-rtt.py helper$$$Renode logs a warning instead of crashing when HDL co-simulated block reports an error$$$improved guest cache tool results readability$$$Fixed:$$$$$$PulseGenerator behavior when onTicks == offTicks$$$External Control API GetTime command returning incorrect results$$$SystemC integration crashing when initializing GPIO connections$$$USB Speed value reported in USB/IP device descriptor$$$USB endpoints with the same number but opposite direction not being distinguished$$$a potential crash due to OverflowException when stopping the emulation$$$checking address range when mapping memory ranges in TranslationCPU$$$configuration descriptor parsing in USBIPServer$$$fatal TCG errors in some cases of invalid RISC-V instructions$$$handling registration of regions not defined by peripherals$$$handling registration of regions with unpaired access method$$$incorrect sequence number in USBIP setup packet reply$$$SD card reset condition$$$starting GDB stub on platforms containing CPUs not supporting GDB$$$infinite loop on debug exception with an interrupt pending$$$simulation elements unpausing after some Monitor commands$$$Added peripheral models:$$$$$$Arm CoreLink Network Interconnect$$$LPC Clock0$$$RenesasDA14 GeneralPurposeRegisters$$$STM32 SDMMC$$$Synopsys SSI$$$Improvements in peripherals:$$$$$$Arm Signals Unit$$$CAES ADC$$$Gaisler FaultTolerantMemoryController$$$LPC USART$$$MiV CoreUART$$$NXP LPUART$$$RenesasDA Watchdog$$$RenesasDA14 ClockGenerationController$$$RISC-V Platform Level Interrupt Controller$$$STM32 DMA$$$ZynqMP IPI$$$ZynqMP Platform Management Unit

Added and improved architecture support:$$$$$$fixed Arm MPU skipping access checks for MPU regions sharing a page with a background region$$$FPU dirty flag is now set on all FPU load instructions for RISC-V$$$fixed Arm PMSAv8 not checking for domains not being page aligned$$$RISC-V MTVAL register now contains the invalid instruction after illegal instruction exception$$$Arm SRS (Store Return State) instruction now saves onto stack SPSR instead of masked CPSR$$$improved support for x86-64; verified with Zephyr$$$added SMEPMP extension stub for RISC-V$$$added ability to configure usable bits in RISC-V PMPADDR registers$$$fixed runtime configurability of the RISC-V MISA registers$$$fixed RISC-V PMPCFG semantics from WIRI to WARL$$$fixed decoding of C.ADDI4SPN in RISC-V$$$fixed behavior of RORIW; RORI and SLLI.UW RISC-V instructions$$$changed MSTATUS RISC-V CSR to be more responsive to the presence of User and Supervisor modes$$$Added and improved platform descriptions:$$$$$$NXP MR-CANHUBK3$$$NXP S32K388$$$NXP S32K118$$$RI5CY$$$Renesas r7fa8m1a$$$Renesas DA14592$$$STM32H743$$$x86-64 ACRN$$$Added demos and tests:$$$$$$Zephyr running hello_world demo on x86-64 ACRN$$$ZynqMP demo showcasing two way communication between Cortex-A53 running Linux and Cortex-R5 running OpenAMP echo sample$$$Added features:$$$$$$Socket Manager mechanism; organizing socket management in a single entity$$$test real-time timeout handling mechanism in Robot$$$GPIO events support for the External Control API$$$Zephyr Mode support for Arm; Arm-M; SPARC; x86 and Xtensa$$$disassembling support for x86-64 architecture$$$support for bus access widths other than DoubleWord for DPI integration of APB3$$$support for overriding a default implementation of the verilated UART model$$$Changed:$$$$$$improved renesas-segger-rtt.py helper$$$Renode logs a warning instead of crashing when HDL co-simulated block reports an error$$$improved guest cache tool results readability$$$Fixed:$$$$$$PulseGenerator behavior when onTicks == offTicks$$$External Control API GetTime command returning incorrect results$$$SystemC integration crashing when initializing GPIO connections$$$USB Speed value reported in USB/IP device descriptor$$$USB endpoints with the same number but opposite direction not being distinguished$$$a potential crash due to OverflowException when stopping the emulation$$$checking address range when mapping memory ranges in TranslationCPU$$$configuration descriptor parsing in USBIPServer$$$fatal TCG errors in some cases of invalid RISC-V instructions$$$handling registration of regions not defined by peripherals$$$handling registration of regions with unpaired access method$$$incorrect sequence number in USBIP setup packet reply$$$SD card reset condition$$$starting GDB stub on platforms containing CPUs not supporting GDB$$$infinite loop on debug exception with an interrupt pending$$$simulation elements unpausing after some Monitor commands$$$Added peripheral models:$$$$$$Arm CoreLink Network Interconnect$$$LPC Clock0$$$RenesasDA14 GeneralPurposeRegisters$$$STM32 SDMMC$$$Synopsys SSI$$$Improvements in peripherals:$$$$$$Arm Signals Unit$$$CAES ADC$$$Gaisler FaultTolerantMemoryController$$$LPC USART$$$MiV CoreUART$$$NXP LPUART$$$RenesasDA Watchdog$$$RenesasDA14 ClockGenerationController$$$RISC-V Platform Level Interrupt Controller$$$STM32 DMA$$$ZynqMP IPI$$$ZynqMP Platform Management Unit